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[转载]【电子技术】【2019.07】虚拟嵌入式设计测试环境中STM32控制器的软件仿真

已有 178 次阅读 2021-9-5 19:50 |系统分类:科研笔记|文章来源:转载

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本文为荷兰埃因霍温工业大学(作者:Joshi, C.V.)的硕士论文,共117页。

 

将仿真硬件集成到嵌入式测试环境中有助于在嵌入式软件开发生命周期(EDLC)的初始阶段对嵌入式软件(ESW)进行迭代和模块化测试。仿真技术消除了对硬件的依赖性,方便了ESW测试,以便在ESW开发的早期阶段识别缺陷。硬件仿真已经在工业中使用Verilog和像HILO这样的硬件设计模拟器来测试硬件设计。在制造硬件芯片之前进行的大量硬件设计测试被证明是具有成本效益的,并且可以节省硬件设计和开发的工作量。近年来,嵌入式设备的软件仿真取得了一些进展,为嵌入式SDLC铺平了道路。

 

本文针对嵌入式系统测试,对现有的验证技术及其存在的不足进行了详细的研究。在此基础上,由Fabrice Ballard QEMU在开源平台上实现了STM32f407ve控制器仿真。QEMU提供必要的API来开发和使用仿真硬件板来实现虚拟化。自由职业者已经在QEMU上完成了构建各种板卡的初步工作,这些板卡被用于本项目,为Vanderlande的测试环境开发特定的STM32板。开发过程包括在QEMU中加入STM32的硬件仿真,仿真外围设备时钟控制和GPIO。对仿真硬件进行了测试,以了解与功能测试、基于时间的测试、CPU负载有关的行为和性能,并与实际硬件进行了比较。本论文提出了一种将虚拟测试环境应用于嵌入式SDLC的观点。

 

Integrating the emulated Hardwareinto the embedded test environment facilitates iterative and modular testing ofEmbedded SoftWare (ESW) at the initial phases of the ESW Development Life Cycle(EDLC). Emulation technology eliminates the dependency on hardware andfacilitates ESW testing to identify the defects in the early stages of ESWDevelopment. Hardware emulation has been around in the industry for testing thehardware design using Verilog & hardware design simulators like HILO.Significant amounts of hardware design testing carried out before thefabrication of hardware chips has proven to be cost effective and saving effortfor the hardware design and development [40]. Recently, there have beenadvancements in the software emulation for Embedded devices paving its way intoEmbedded SDLC [1]. In this thesis, a detailed study is conducted on theexisting verification techniques and their drawbacks with respect to theembedded system testing. Based on this study, an implementation of theSTM32f407ve controller emulation is carried out on an open-source platform byFabrice Ballard-QEMU [9]. QEMU provides essential APIs to develop and use theemulated hardware board to achieve virtualization. Initial work has beencarried out by freelancers on QEMU to build various boards, which have been referredfor this project to develop the specific board of STM32 for the testenvironment at Vanderlande. The development includes adding the hardwaremachine emulation of STM32 to the QEMU with the emulated peripherals clockcontrol and GPIO. The emulated hardware has been examined to understand thebehavior and performance concerning the functional testing, time-based testing,CPU load as compared to the real hardware. This thesis initiates a view towardsutilizing the virtual test environments for Embedded SDLC over traditional testsetups.

 

1.       引言

2. 项目背景

3. 基础知识

4. 硬件仿真评估

5.STM32F407硬件仿真的具体实现

6. 硬件仿真平台的性能分析与评估

7. 结论

附录AQEMU开发

附录BSTM32硬件的具体实现

附录性能分析



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