本文为加拿大多伦多大学（作者：Tomasz Sebastian Czajkowski）博士论文，共150页。

现场可编程门阵列（FPGA）是一种可配置的实现各种逻辑电路的平台。它通过逻辑元件（通常是查找表）实现电路，逻辑元件通过可编程路由网络连接。为了有效利用FPGA，开发了计算机辅助设计（CAD）工具。这些工具通过使用传统的CAD流程来实现电路，在该流程中，对电路进行分析、综合、技术映射，最后将其放置在FPGA结构上布线。这个流程虽然通常是有效的，但会产生次优的结果，因为一旦流程的某个阶段完成，就不会重新进行优化。这个问题是通过一个已知物理综合的增强流来解决的，它由传统流的一组迭代构成，一个关键区别是：每次迭代的结果直接影响下一次迭代的结果。因此，可以对优化进行再次评估，然后在接下来的迭代中根据需要进行调整，从而得到总体上更好的实现。

这种CAD流很难处理，因为对于给定的FPGA，研究人员需要以迭代的方式访问流的每个阶段。这在瞄准现代商用FPGA时尤其具有挑战性，因为现代商用FPGA比学术界通常使用的简单查找表和触发器模型复杂得多。本文描述了一个统一的框架，称为物理综合工具包（PST），用于研究和开发现代FPGA器件的优化。PST提供了访问现代FPGA设备和CAD工具流的途径，以方便研究。同时，使框架适应新的FPGA设备所需的工作量保持在最低限度。为了证明PST是一个有效的研究平台，本文描述了PST内部实现的优化和建模技术。

优化包括：在基于4-LUT的FPGA上实现的基于XOR的逻辑电路面积缩减技术（25.3%的面积缩减），以及在Altera Stratix II FPGA上实现的电路中减少故障的动态功率降低技术（7%的动态功率降低）。该建模技术是一种新的基于异或分解的切换速率估计方法，与Altera QuartusⅡ CAD工具的最新版本相比，估计误差降低了37%。

A Field-Programmable Gate Array (FPGA) is a configurable platform for implementing a variety of logic circuits. It implements a circuit by the means of logic elements, usually Lookup Tables, connected by a programmable routing network. To utilize an FPGA effectively Computer Aided Design (CAD) tools have been developed. These tools implement circuits by using a traditional CAD flow, where the circuit is analyzed, synthesized, technology mapped, and finally placed and routed on the FPGA fabric. This flow, while generally effective, can produce sub-optimal results because once a stage of the flow is completed it is not revisited. This problem is addressed by an enhanced flow known Physical Synthesis, which consists of a set of iterations of the traditional flow with one key difference: the result of each iteration directly affects the result of the following iteration. An optimization can therefore be evaluated and then adjusted as needed in the following iterations, resulting in an overall better implementation. This CAD flow is challenging to work with because for a given FPGA researchers require access to each stage of the flow in an iterative fashion. This is particularly challenging when targeting modern commercial FPGAs, which are far more complex than a simple Lookup Table and Flip-Flop model generally used by the academic community. This dissertation describes a unified framework, called the Physical Synthesis Toolkit (PST), for research and development of optimizations for modern FPGA devices. PST provides access to modern FPGA devices and CAD tool flow to facilitate research. At the same time the amount of effort required to adapt the framework to a new FPGA device is kept to a minimum. To demonstrate that PST is an effective research platform, this dissertation describes optimization and modeling techniques that were implemented inside of it. The optimizations include: an area reduction technique for XOR-based logic circuits implemented on a 4-LUT based FPGA (25.3% area reduction), and a dynamic power reduction technique that reduces glitches in a circuit implemented on an Altera Stratix II FPGA (7% dynamic power reduction). The modeling technique is a novel toggle rate estimation approach based on the XOR-based decomposition, which reduces the estimate error by 37% as compared to the latest release of the Altera Quartus II CAD tool.

1.       引言

2. 项目背景

3. 物理综合工具箱

4. 功能线性分解与综合

5. 降低动态功率

6. 信号切换速率的估计

7. 结论与未来展望

附录A 启发式变量划分算法

附录B 基与选择器优化算法

附录C 多输出合成算法

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