壮志未酬身将死?长使咱家泪满澿。
[小资料] 场效应晶体管 FET:短沟道效应
场效应晶体管: field effect transistor; FET
短沟道效应: short channel effect
三材料栅极: tri-material gate
跨开栅极装置结构: straddle gate device structure
无结晶体管: junctionless transistor
纳米线晶体管: nanowire transistor
超薄体场效应晶体管: extremely thin silicon on insulator field effect transistor; ETSOI
为了证明本科生《电工学》课程的巨大威力,本来想在“电路/集成电路”方面做出个“诺贝尔奖”水平的成果。
可惜实在太累了。脑力不够,今晚是做不出来了。
还木有搞清楚现在的“集成电路/场效应管”,到底有什么缺点?
一、《中国大百科全书》词条“短沟道效应/short channel effect”摘录
https://www.zgbk.com/ecph/words?SiteID=1&ID=124114&Type=bkzyb&SubID=99036
场效应晶体管的沟道长度缩小到与源结和漏结的耗尽层宽度数量级相同后,缓变沟道近似于不再适用,当沟道长度缩小时,场效应晶体管的阈值电压减小的现象。在漏极偏置等于电源电压时,短沟道效应尤其显著。
短沟道效应对器件的影响主要有:阈值电压减小;高场下载流子迁移率下降,载流子速度饱和,与电场无关,饱和电流与栅压呈线性关系;电场强度增强,热载流子增多,影响器件寿命;亚阈值电流增加,静态功耗变大等。
抑制短沟道效应的方法主要有:降低器件工作电压、提高沟道掺杂浓度,利用绝缘体上硅(silicon on insulator,SOI)衬底结构、轻掺杂漏(lightly doped drain,LDD)、非均匀掺杂的Halo离子注入、双栅和多栅场效应晶体管结构等。
二、短沟道效应,百度百科
https://baike.baidu.com/item/%E7%9F%AD%E6%B2%9F%E9%81%93%E6%95%88%E5%BA%94/8604983
短沟道效应(英语:short-channel effects)是当金属氧化物半导体场效应管的导电沟道长度降低到十几纳米、甚至几纳米量级时,晶体管出现的一些效应。
(1)影响阈值电压的短沟、窄沟效应
(2)迁移率场相关效应及载流子速度饱和效应
(3)影响器件寿命的热载流子效应
(4)亚阈特性退化,器件夹不断
三、其它资料的阅读笔记
以下由“机器翻译”将英语译成汉语。
2.1 2016 《FinFET- One Scale up CMOS: Resolving Scaling Issues》 第 1183 页
https://ieeexplore.ieee.org/abstract/document/7724453
the most of which are the short channel effects and leakage currents[2].
最主要的是短通道效应和泄漏电流[2]。
2.2 2012 《Simulation study on FinFET with tri-material gate》 木有页码?
https://ieeexplore.ieee.org/document/6482802
As channel length scaling into nanometer regime, shortchannel effects (SCEs) and hot-carrier effects (HCEs) impose a physical limit on the ultimate performance of traditional planar MOSFET [1].
随着沟道长度扩展到纳米范围,短沟道效应(SCE)和热载流子效应(HCE)对传统平面MOSFET的最终性能施加了物理限制[1]。
2.3 2022 《Recent Trends in Novel Semiconductor Devices》 第 9211 页
https://link.springer.com/article/10.1007/s12633-022-01694-8
In the nanometer regime, increased short channel effects(SCEs) make it difficult to maintain the scaling trend predicted by Moore‘s law [2–4]. A deeply scaled MOSFET has a very narrow channel length because of which the electrostatics of the channel begin to be influenced by drain potential. Therefore, the gate relinquishes sufficient control over the channel. Consequently, the gate is incapable of closing up the channel entirely in the off-mode of working resulting in a higher leakage current between the drain and the source.
在纳米范围内,增加的短通道效应(SCE)使其难以维持摩尔定律预测的缩放趋势[2-4]。深度缩放的MOSFET具有非常窄的沟道长度,因此沟道的静电开始受到漏极电势的影响。因此,闸门放弃了对通道的充分控制。因此,栅极不能在截止工作模式下完全关闭沟道,导致漏极和源极之间的漏电流更高。
2.4 2006 《Modeling and Simulation of a Nanoscale Three-Region Tri-Material Gate Stack (TRIMGAS) MOSFET for Improved Carrier Transport Efficiency and Reduced Hot-Electron Effects》 第 1623 页
https://ieeexplore.ieee.org/document/1643496
AS MOSFET gate lengths are scaled down to sub-100 nm and gate oxide thickness to below 3 nm, short-channel effects (SCEs) such as: 1) increase in effective gate oxide thickness (EOT) due to polysilicon gate depletion; 2) threshold voltage change due to boron penetration from p+ polysilicon gate into the channel region; 3) degradation of device reliability due to gate leakage current (hot-electron effects); and 4) reduced gate controllability due to drain-induced barrier lowering (DIBL) become predominant. These SCEs [1] need to be eliminated or minimized for proper device operation.
To eliminate polysilicon depletion width effects and polysilicon dopant penetration, polysilicon gates need to be replaced by metal gates.
AS MOSFET栅极长度缩减至低于100nm,栅极氧化物厚度缩减至低于3nm,短沟道效应(SCE)例如:1)由于多晶硅栅极耗尽导致有效栅极氧化物厚度(EOT)增加;2) 由于硼从p+多晶硅栅极渗透到沟道区域中而引起的阈值电压变化;3) 由于栅极漏电流(热电子效应)导致的器件可靠性下降;以及4)由于漏极引起的势垒降低(DIBL)而导致的栅极可控性降低成为主要原因。这些SCE[1]需要消除或最小化,以确保设备正常运行。
为了消除多晶硅耗尽宽度效应和多晶硅掺杂剂渗透,多晶硅栅极需要用金属栅极代替。
2.5 2023 《UTBB SOI MOSFETs 短沟道效应抑制技术》第 392 页
随着CMOS 技术的飞速发展,为了提高集成电路的性能,加快器件的工作速度并降低其功耗,根据R. H. Dennard 等人提出的缩放比例定律[1],晶体管的特征尺寸不断缩小,目前技术节点已缩至10 nm以下,但也面临越来越多的挑战,尤其是短沟道效应(Short channel effects,SCEs)。此时仅仅依靠提高沟道掺杂浓度、减薄硅层厚度、降低源漏的结深等方法已不足以解决小尺寸器件的SCEs。为了延续摩尔定律,必须探究材料和器件结构层面的创新,有效的解决方案是提高器件的栅控能力,例如全耗尽绝缘体上硅(Fully depleted silicon on insulator,FD SOI)[2]、鳍式场效应晶体管(FinFET)[3]、全环绕栅极晶体管(Gate-all-around field effect transistor,GAAFET)[4]等。
参考资料:
[1] 2022-01-20,短沟道效应/short channel effect/孙兵,中国大百科全书,第三版网络版[DB/OL]
https://www.zgbk.com/ecph/words?SiteID=1&ID=124114&Type=bkzyb&SubID=99036
[2] Wei Cao, Huiming Bu, Maud Vinet, Min Cao, Shinichi Takagi, Sungwoo Hwang, Tahir Ghani, Kaustav Banerjee. The future transistors [J]. Nature, 2023, 620(7974): 501–515. 16 August 2023
doi: 10.1038/s41586-023-06145-x
https://www.nature.com/articles/s41586-023-06145-x
[3] Archana Pandey. Recent Trends in Novel Semiconductor Devices [J]. Silicon, 2022, 14(15): 9211–9222.
doi: 10.1007/s12633-022-01694-8
https://link.springer.com/article/10.1007/s12633-022-01694-8
[4] Kirti Goel, Manoj Saxena, Mridula Gupta, R. S. Gupta. Modeling and simulation of a nanoscale three-region tri-material gate stack (TRIMGAS) MOSFET for improved carrier transport efficiency and reduced hot-electron effects [J]. IEEE Transactions on Electron Devices, 2006, 53(7): 1623-1633.
doi: 10.1109/TED.2006.876272
https://ieeexplore.ieee.org/document/1643496
[5] D. Sudha, C. H. Santhirani, Sreenivasa Rao Ijjada, Sushree Priyadarsinee. FinFET — One scale up CMOS: Resolving scaling issues [C]. 2016 3rd International Conference on Computing for Sustainable Global Development (INDIACom), 2016: 1183-1187.
doi: 木有?
https://ieeexplore.ieee.org/abstract/document/7724453
[6] Cong Li, Yiqi Zhuang, Li Zhang. Simulation study on FinFET with tri-material gate [C]. 2012 IEEE International Conference on Electron Devices and Solid State Circuit (EDSSC), 2012: 木有页码? 978-1-4673-5696-1/12/$26.00 ©2012 IEEE
doi: 10.1109/EDSSC.2012.6482802
https://ieeexplore.ieee.org/document/6482802
[7] Taikyu Kim, Cheol Hee Choi, Jae Seok Hur, Daewon Ha, Bong Jin Kuh, Yongsung Kim, Min Hee Cho, Sangwook Kim, Jae Kyeong Jeong. Progress, Challenges, and Opportunities in Oxide Semiconductor Devices: A Key Building Block for Applications Ranging from Display Backplanes to 3D Integrated Semiconductor Chips [J]. Advanced Materials, 2023, 35(43)Special Issue SI: 2204663.
doi: 10.1002/adma.202204663
https://onlinelibrary.wiley.com/doi/10.1002/adma.202204663
[8] 李曼, 张淳棠, 刘安琪, 姚佳飞, 张珺, 郭宇锋. UTBB SOI MOSFETs 短沟道效应抑制技术[J]. 固体电子学研究与进展, 2023, 43(5): 392-400.
doi: 0.19623/j.cnki.rpsse.2023.05.012
相关链接:
[1] 2023-11-17,[小资料] 场效应晶体管 FET:多材料栅极
https://blog.sciencenet.cn/blog-107667-1410052.html
[2] 2023-11-13,[打听] 继晶体管、集成电路之后,电路重大突破会出现在哪里?
https://blog.sciencenet.cn/blog-107667-1409521.html
[3] 2023-11-14,[打听] 哪些新型半导体器件是未来的主流?
https://blog.sciencenet.cn/blog-107667-1409653.html
[4] 2023-11-15,[悲恸,绝望,崩溃] 创新,有时会气死人吗?(霍尔尼 Hoerni 的平面工艺 planar)
https://blog.sciencenet.cn/blog-107667-1409771.html
[5] 2023-09-09,[小资料] FinFET(鳍式场效应晶体管 fin field effect transistor)
https://blog.sciencenet.cn/blog-107667-1402038.html
[6] 2023-09-07,[小资料] 1966年鲍尔(Robert W. Bower)申请的 MOSFET 自对准栅极工艺专利(图片)
https://blog.sciencenet.cn/blog-107667-1401852.html
[7] 2023-09-06,[小资料] 1963年万拉斯(Frank Marion Wanlass)、萨支唐(Chih-Tang Sah)申请的CMOS专利和论文(图片)
https://blog.sciencenet.cn/blog-107667-1401741.html
[8] 2023-09-05,[小资料] 1963年霍夫施泰因(Steven R. Hofstein)、海曼(Frederic Paul Heiman)的MOS场效应管论文(部分图片)
https://blog.sciencenet.cn/blog-107667-1401577.html
[9] 2023-09-04,[小资料] 1960年阿塔拉(Martin (John) M. Atalla)、江大原(Dawon Kahng)申请的MOS场效应管专利(图片)
https://blog.sciencenet.cn/blog-107667-1401453.html
[10] 2023-09-02,[小资料] 1935年海尔(Oskar Heil)的场效应管专利(图片)
https://blog.sciencenet.cn/blog-107667-1401242.html
[11] 2023-09-01,[小资料] 1926年利林费尔德(Julius Edgar Lilienfeld)的场效应半导体专利(图片)
https://blog.sciencenet.cn/blog-107667-1401136.html
[12] 2023-08-11,[怀旧,回顾,展望] 二极管与非门,场效应晶体管
https://blog.sciencenet.cn/blog-107667-1398708.html
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