本文为美国科罗拉多州大学（作者：Rajbharath Chandramohan）的硕士论文，共65页。

硬件加速器是高度优化的功能模块，旨在以更高的性能执行特定任务。我们为Jacobi二维和Wave二维算法开发了一个硬件加速器，这两种算法都使用模板模式进行计算。它们被用于声学、电磁学和流体力学领域的许多科学应用。这些问题具有较大的问题求解、内存限制和带宽限制，导致运行时间过长。因此，有必要采用一种方法来提高解决这些问题的性能，从而降低带宽需求。 

我们建立了Wave-2D算法和Jacobi-2D算法性能、带宽和面积的分析模型，并利用MATLAB和Excel对其进行了求解。为了达到最佳设计，我们将计算分为两个层次。第一层称为passes，它是一个穿过三维迭代空间的长方体。每个过程都映射到硬件加速器中的处理元素（PE）网格。第二级平铺将垂直长方体拆分为由单个PE执行的较小长方体。这些优化在用Verilog设计的硬件加速器中实现，并用ModelSIM进行了仿真。ModelSIM的仿真结果提供了一个精确的模型和设计的实验验证。我们还提高了处理性能，降低了带宽。

Hardware accelerators are highly optimized functional blocks designed to perform specific tasks at higher performance. We developed a hardware accelerator for Jacobi 2D and Wave 2D algorithms, two computations with a stencil pattern. They are used in many scientific applications in the field of acoustics, electro magnetics and Fluid dynamics. These problems have large problem sizes, memory limitations and bandwidth constraints that result in long run times. Hence, an approach which increases the performance of these problems that reduces bandwidth requirement is necessary. We developed analytical models for the performance, bandwidth and area models for the Wave 2D algorithm and Jacobi 2D algorithm and solved them for the optimal solution using posynomials and positivity property in MATLAB and using Excel Solver. In order to achieve an optimal design, we split the computation into two levels of tiling. The first level called passes is a rectangular prism that runs through the 3-D iteration space. Each pass is mapped to a grid of processing elements(PEs) in the hardware accelerator. The second level of tiling splits the vertical prism into smaller prisms executed by a single PE. These optimizations are implemented in the hardware accelerator designed using Verilog and simulated using ModelSIM. Results from ModelSIM provides an accurate model and an experimental verification of the design. We also achieved improved performance and lower bandwidth.

1.       引言

2. 项目背景

3. Wave 2D加速器设计

4. Jacobi 2D加速器设计

5. 硬件设计

6. 最优化问题

7. 结论与展望

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